A semiconductor storage device in which a cell array is constituted by dynamic memory cells requiring refresh for data retention and which functions as a static random-access memory (SRAM) (such a storage device is also referred to as “pseudo SRAM”) has come into use in recent times. A Mobile Specified RAM Family (also referred to as an “MSRAM”) also has been developed. An MSRAM is functionally compatible with a low-power-consumption SRAM and achieves a large increase in capacity (e.g., 16 to 128 M), which is not possible with an SRAM, by employing a DRAM (Dynamic Random-Access Memory) memory cell.
FIG. 8 is a diagram illustrating an example of dynamic operation of a burst mode (burst length=8) in a clock-synchronized semiconductor storage device (synchronous DRAM, or “SDRAM”). The SDRAM is characterized by the following:
it has an SDR (single data rate) of a clock frequency of 133 MHz;
the burst length (word length of successively output data) is 8 bits, 16 bits (one word) parallel;
the CAS latency (number of clocks from input of a read command to output of the initial valid data) is 3; and
the time needed to transfer an 8-word burst is 120 ns.
In FIG. 8, CLK represents a synchronizing clock signal, CMD/Add denotes a command/address signal, and Dout/Din represents a data signal at a data input/output terminal. A bank active command (ACT) and a row address are input and the bank is activated. Upon elapse of a predetermined cycle period (tRCD, e.g., 30 ns=four clock cycles), a read command (RD) and a column address are input. Word data QA0 to QA7 having a burst length set by a mode register and an address designated in accordance with /CAS latency (CL=3) is output. PRE represents a precharge command. In the example shown in FIG. 8, one clock cycle is equal to 7.5 ns, and the period of time from the ACT command to the next ACT command is 120 ns.
In an SDRAM the timing operation of which is exemplified in FIG. 8, the cycle that occupies the memory core is long owing to the continuation of row access. Further, one access cycle requires three commands, namely the active command (ACT), the read/write command (RD) and the precharge command (PRE). Furthermore, refresh control from an external SDRAM controller is required. The number of pins is reduced by address multiplexing of the row and column addresses (RAS, CAS).
FIG. 9A illustrates an example of operation of an MSRAM of SRAM interface specifications in which the cell array is constituted by a DRAM. An SDRAM the timing operation of which is exemplified in FIG. 9A is characterized by the following:
it has an SDR (single data rate) of a clock frequency of 133 MHz;
the burst length is 8 bits, 16 bits (one word) parallel;
the rate latency (RL) is 7; and
the time needed to transfer an 8-word burst is 112.5 ns.
In this MSRAM, a WAIT signal is output as the active state when conflict occurs with internal refresh at the instant a chip-select signal /CS (low active) undergoes a transition from the high to the low level. It should be noted that precharging is performed automatically in the MSRAM.
As illustrated in FIG. 9A, the time required for transfer of an 8-word burst is 112.5 ns, which is one to two cycles faster in comparison with the SDRAM of FIG. 8. Further, in a semiconductor storage device having the timing operation illustrated in FIG. 9A, a decline in performance ascribable to refresh basically is nil.
FIG. 9B illustrates an example of operation in a case where addresses and data are multiplexed in an MSRAM. FIG. 9B illustrates an example of timing operation in a burst mode (burst length=8) of a clock-synchronized semiconductor storage device in which part of an address terminal is shared with a data terminal to achieve multiplexing. The clock signal CLK is the same as that used in FIG. 9A. In FIG. 9B, ADV represents a signal indicating the validity of an address signal supplied from an address bus to a shared access/data terminal ADD/Data of the MSRAM. In response to activation of ADV, the MSRAM latches the address signal at the shared access/data terminal ADD/Data by a register. From this point onward, the shared access/data terminal ADD/Data functions as a data input/output terminal. In a case where an address and data are used by being multiplexed at a common terminal, the number of pins is reduced in comparison with an SDRAM when the number of data terminals is greater than 32. In the example shown in FIG. 9B, the shared access/data terminal ADD/Data, acting as a data output terminal, outputs readout data QA0 to QA7 in the burst mode.
FIG. 10 is a diagram illustrating the operation of an MSRAM having SRAM interface specifications and equipped with a pipeline burst function. In FIG. 10, CLK represents a synchronizing clock, CMD/Add denotes a command/address signal, and Dout/Din represents a data signal at a data input/output terminal. In this implementation, read commands RDA, RDB, and RDC are input, 8-word successive data QA0 to QA7 corresponding to the read command RDA is output upon a delay equivalent to the CAS latency, 8-word successive data QB0 to QB7 corresponding to the read command RDB is output from the next clock cycle of the output of data QA7, and 8-word successive data QC0 to QC7 corresponding to the read command RDC is output from the next clock cycle of the output of data QB7. After the read command RDA is input, readout data (8 words×3) of the read commands RDA, RDB and RDC are output successively upon elapse of prescribed clock cycles (e.g., 60 ns). Thus, after a read command is input, burst data is output upon elapse of a fixed period of time. In the meantime, while data corresponding to the previous read command is being output, the next command is received. Successive data output is made possible by a random-access address.
It should be noted that the specification of following Patent Document 1 (FIG. 1) discloses a semiconductor memory, which has at least one multiplexing signal input terminal serving as a terminal for inputting both a data signal and an address signal. A control signal (address-enable signal) for identifying whether a signal applied to the multiplexing signal input terminal is a data signal or an address signal.
[Patent Document 1]
JP Patent Kokai Publication JP-A-11-328971
In the semiconductor storage device having the pipeline burst function depicted in FIG. 10, the arrangement is such that while data corresponding to a read command is being output, the next command is received. Read-out data in 8-word units can be output successively without interruption.
However, after the initial read command RDA is input, data is not output to the data terminal for the duration of the latency period and an idle state results. The Inventor has discovered that an even higher speed can be achieved by utilizing this idle state effectively and has accomplished the present invention based upon this discovery.